module timer (clk, r, en, done);
    parameter n = 12; 
    parameter counter_bits = 4;

    input clk, r, en;
    reg [counter_bits-1:0] q = 0;
    output done;
    reg done = 0;

    always @(posedge clk) begin
        if ( r )    
            q = 0;
        else if (en)    
            q = q+1;
        done = en && (q==n-1);
    end
endmodule